(1) Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices used for semiconductor integrated circuits, liquid crystal panels, etc. More particularly, the present invention relates to a method for manufacturing semiconductor devices with use of an electron beam projection method that is a lithographic technique employed for forming fine patterns of the semiconductor devices, as well as a method for forming the masks used by the method and a method for generating data for the masks.
(2) Description of the Related Art
Lithographic techniques are usually employed for forming patterns of semiconductor integrated circuits, etc. And, a light, an electron beam, or the like is used as the energy beam. The photo-lithography among those lithographic techniques has been improved in resolution by changing the wavelength of the light source from a g-line (436 nm) to such short wavelengths as an i-line (365 nm) and a KrF (248 nm). However, performance of such the photo-lithography is now coming to become too insufficient to satisfy a pattern dimension required as device performance. The wavelengths of light sources are thus further required to become shorter to improve the resolution ability. To meet such the requirement, however, a huge amount of development cost is needed to develop not only the light source but also lens glass materials and resists. The equipment and process costs also rise, which will then result in significant rising of the costs of the semiconductor devices manufactured with use of those lenses and resists.
On the other hand, the electron beam lithography is higher in resolution than the photo-lithography while the conventional electron beam lithographic equipment have not been suited for mass production of semiconductor devices because of the throughput, since each of them applies a point beam all over the target resist completely or scans patterns having a size of several micrometers (μm) square or so, which are connected to one after another.
One of the methods proposed for improving this electron beam lithography throughput is disclosed, for example, in “Japanese Journal Applied Physics, vol. 39 (2000)), pp. 6897 to 6901”. According to the method, all the patterns formed on the entire surface of a target chip are generated as an original mask (hereinafter, to be referred to as a mask) and an electron beam is irradiated to this mask to project/print those patterns on the wafer. The method is referred to as the Electron Projection Lithography. This method is similar to the photo-lithography in the aspect of the projection of a beam. The method differs from the photo-lithography only in that the light source is changed to an electron beam, although the throughput is improved by one figure to 35 (8-inch wafers)/hour from the conventional electron beam lithography.
The shape of this electron beam printing mask is shown, for example, in “Proceedings of SPIE, vol. 3997 (2000), pp. 214 to 224”. FIG. 2A shows a bird's eye view of the electron beam printing mask, FIG. 2B shows an expanded view of the mask shown in FIG. 2A, and FIG. 2C shows a top view of the mask. According to the electron projection lithography, a circuit pattern of an LSI chip is divided into a plurality of 1000 μm square regions, which are then connected to one another when in printing to form a pattern of the entire chip. Hereinafter, one of the divided regions, that is, a region to be printed at once will be referred to as a “subfield” 201. Connection of one subfield to another is done by moving both wafer and mask stage mechanically and synchronously and/or polarizing the electron beam. The silicon layer of the pattern region in each subfield 201 is as thin as 0.5 to 2 μm and fragile. Thus, a beam referred to as a strut 202 is disposed between subfields to improve the mechanical strength thereof.
Hereunder, a method for manufacturing the electron beam printing mask will be described with reference to a flowchart shown in FIGS. 3A to 3D. As shown in FIG. 3A, it is assumed here that a SOI (Silicon On Insulator) wafer in which an SiO2 layer is disposed between silicon layers is used. The silicon substrate SUB is about 400 μm to 800 μm in thickness. On the substrate are formed an SiO2 film of 0.1 μm, to 0.5 μm in thickness and a silicon film of 0.5 to 2 μm in thickness respectively. There are two etching methods employed for manufacturing the above electron beam printing mask; a pre-back-etching method for etching the back side of a substrate to form the strut 202 before mask patterning and a post-back-etching method for etching the back side of the substrate after the mask patterning. In this case, the pre-back-etching method will be described. The pre-back-etching method performs resist patterning to form the struts 202 at the back side of the substrate first, then the back side of the silicon substrate is etched by means of dry-etching. When the SiO2 is removed, the membrane blanks to be used for the electron beam printing mask appears as shown in FIG. 3B. Then, a resist pattern 204 is formed at the back side (opposite side of the struts 202) of this membrane blanks (FIG. 3C). After this, the silicon film is removed from the substrate surface by means of dry-etching, thereby forming of the above electron beam printing mask is completed (FIG. 3D).
If a stencil type mask is used in the electron beam projection equipment at this time, it is impossible to form any non-irradiation region enclosed completely by an electron beam exposed region (aperture pattern of the mask). In addition, if the aperture ratio rises, the non-aperture region is reduced in size, thereby the mask's mechanical strength is lowered. If the aperture ratio is high, the value of the mask transmission current that passes the mask's apertures to be irradiated on the target wafer increases, thereby the Coulomb interaction works between electrons to cause a beam blur on the wafer.
In order to solve the above problem, there is a method proposed, which prints patterns in one region on a wafer by a plurality of times with the electron beam using so-called complementary masks obtained by dividing, those patterns into groups to be put into two or more masks.
The official gazette of Japanese Patent Laid-open No. H8 (1996)-236428 discloses another method for printing patterns in a target region multiply using two masks; one mask is constituted by edges of a large pattern and the other mask is constituted by the inside portion of the large pattern and fine patterns.
Furthermore, the official gazette of Japanese Patent Laid-open No. H11 (1999)-204422 discloses still another method for exposing patterns by dividing an original mask into a wide pattern mask and a narrow pattern mask, then increasing the exposure dose for the narrow pattern mask.
The entire disclosure of Japanese Patent Application No. 2001-153351 (U.S. application Ser. No. 10/083417) and Japanese Patent Application No. 2001-282546(U.S. application Ser. No. 10/171769) including specification, claims, drawings and summary are incorporated herein by reference in its entirety.